Make Files - In C or C++

Introduction

The make command is useful for the automatic generation of programs (or other things such as latex documents!). Make figures out how to compile a program based on its "Makefile", by convention the Makefile is named just that with out any extension and located in the directory with the source. When running make, it looks for this file to compile the program. Alternatively the -f option will tell make to look for another makefile with a different name as specified.

A sample Makefile:

all: data.o io.o main.o
      gcc data.o io.o main.o .o myexecutable

data.o: data.c data.h
      gcc .c data.c

io.o: io.c io.h
      gcc .c io.c

main.o: main.c data.h io.h common.h
      gcc .c main.c

clean:
      rm *.o myexecutable

Note: Make sure you use tabs before the commands and not spaces!

Compilation Basics

Before getting into the details of how make works lets cover the basics of how programs are compiled and linked to create the final executable binary. When compiling a simple program there is at least one .c source file and possible several .h header files. In this case, as depicted in figure 1, compiling the program requires one command such as "gcc <your source>.c .o <your executable binary>".

As the project grows in size it makes sense to divide your source code into separate easily-manageable .c source files. Figure 2 depicts how to compile multiple source files with one command such as "gcc <your source 1>.c <your source 2>.c .o <your executable binary>".

The steps taken to create an executable program may be split up into several steps, this way when changing one file only that file needs to be recompiled and then the program linked again. This can save time by eliminating the recompilation of unchanged source files that occurred in the previous versions. Figure 3 depicts how to compile multiple source files in separate steps. Inside the red circle source files are compiled into object files with a .o extension using a command such as "gcc .c <your source>.c". This command is repeated several times for each source file in your project. Once all the source files have been compiled they only need to be linked together to create the executable binary file. You may use a command such as "gcc <your object file 1>.o <you object file 2>.o .o <your executable binary file>".

How make uses the Makefile

Make uses a series of dependencies to describe how to compile a program list in the Makefile. The dependencies state what operations need to occur when a specific file is updated. Figure 4 depicts a dependency graph for a small project generated by a Makefile.

The make program analyzes the dependency graph from the Makefile and checks the modification time for each element in the graph. When ever a file is "newer" than something that depends upon it, make then runs the corresponding command for that dependency. In the example shown in red, the compilation of data.c and the linkage of data.o, main.o, and io.o are the only operations that need to be preformed.

The Makefile is a list of dependencies and a command to update a file in a specific format. The format to describe a dependency is:

<target> : <source files(s)>
<tab>   <command>
  

When the listed <source file(s)> have a newer modification time than the <target> then the <command> is executed. Figure 5 lists our sample project and it's make file corresponding to each dependency listed in the file.